SPRITE, INC.

SM 486-50UVL

Processor        80486SX/80487SX/80486DX/ODP486SX/80486DX2
Processor Speed  25/33/40/50(internal)/50/66(internal) MHz
Chip Set         OPTI
Max. Onboard DRAM32MB
Cache            64/128/256KB
BIOS             MR
Dimensions       330mm x 220mm
I/O Options      32-bit VESA local bus slots (3)
NPU Options      None

[Image]

                                CONNECTIONS

  Purpose                Location      Purpose                Location

  Turbo LED                 J1         Power LED &               J5
                                       keylock

  Speaker                   J2         Turbo switch              JP6

  External battery          J3         32-bit VESA local     S1, S2, & S3
                                       bus slots

  Reset switch              J4

                        USER CONFIGURABLE SETTINGS

                 Function                      Jumper         Position

  »   CPU speed select iOSC/2                    W3            Closed

      CPU speed select iOSC/1                    W3             Open

  »   System password enabled/Monitor            W14           Closed
      type select monochrome

      System password disabled/Monitor             W14            Open
      type select color

  »   Battery select internal                    W15           Closed

      Battery select external                      W15            Open

  »   Factory configured - do not alter          W16          Unknown

  »   Factory configured - do not alter          W17          Unknown

  VESA BUS SPEED (ID3) CONFIGURATION

     CPU speed          JP1 (ID3)

      £ 33MHz              Open

      > 33MHz             Closed

             32-BIT VESA LOCAL BUS AVAILABILITY CONFIGURATION

       CPU Speed             Slots Available                JP2

        £ 50MHz               S1, S2, & S3           pins 2 & 3 closed

         66MHz                     S3                pins 1 & 2 closed

  Note: Board speed of 66MHz is an optional upgrade available through the
  manufacturer.

                           CACHE CONFIGURATION

     Size          Cache         Location         TAG         Dirty Bit

     64KB        (8) 8K x 8    Banks 0 & 1    (1) 8K x 8     (1) 16K x 4

     128KB      (4) 32K x 8       Bank 0      (1) 8K x 8     (1) 16K x 4

     256KB      (8) 32K x 8    Banks 0 & 1    (1) 32K x 8    (1) 16K x 4

                        CACHE JUMPER CONFIGURATION

  Size     W6   W7      W8        W9       W10       W11     W12     W13

  64KB     1 &  1 &    Open      Open     Open      Open     Open     1 &
           2     2                                                    2

  128KB    1 &  2 &    Open     Closed    Open      Closed   1 & 2    2 &
           2     3                                                    3

  256KB    2 &  2 &    Closed   Closed    Closed    Closed   2 & 3    1 &
           3     3                                                    2

  Note: Pins designated should be in the closed position.

                          CPU TYPE CONFIGURATION

          CPU type                    W1                      W2

          80486SX              pins 2 & 3 closed             Open

      80487SX/ODP486SX         pins 1 & 2, 3 & 4      pins 2 & 3 closed
                                    closed

      80486DX/80486DX2         pins 1 & 2, 3 & 4      pins 1 & 2 closed
                                    closed

              DRAM CONFIGURATION

      Size          Bank 0          Bank 1

      1MB         (4) 256K x 9       NONE

      2MB         (4) 256K x 9   (4) 256K x 9

      4MB         (4) 1M x 9         NONE

      5MB         (4) 256K x 9    (4) 1M x 9

      8MB         (4) 1M x 9      (4) 1M x 9

      16MB        (4) 4M x 9         NONE

      17MB        (4) 256K x 9    (4) 4M x 9

      20MB        (4) 1M x 9      (4) 4M x 9

      32MB        (4) 4M x 9      (4) 4M x 9